In view of the increasing demands for electronic products that have miniaturized profiles and are capable of operating at high speeds, it is considered necessary to improve the performance and capacity of a single semiconductor package for use in a miniaturized electronic product. Accordingly, the single semiconductor package is intended to incorporate two or more semiconductor chips to form a multi-chip module with desirably reduced overall circuit size and enhanced electrical functionality.
FIG. 1 shows a multi-chip semiconductor package disclosed in U.S. Pat. No. 5,793,108. This semiconductor package comprises a lead frame 10 having a die pad 100 and a plurality of leads 101; a first chip 11 attached to the die pad 100 via an insulating tape 13, and electrically connected to inner ends of the leads 101 of the lead frame 10 by bonding wires 15; a second chip 12 attached to the first chip 11 via an insulating adhesive layer 14 in a back-to-back manner, and electrically connected to the inner ends of the leads 101 of the lead frame 10 by bonding wires 16, such that the first and second chips 11, 12 can be electrically connected to an external device (not shown) by means of the leads 101; and an encapsulant 17 for encapsulating the first chip 11, the second chip 12 and the inner ends of the leads 101 so as to prevent external moisture and contaminants from invading the first and second chips 11, 12.
The above semiconductor package however encounters a problem of having delamination between the first chip and the die pad. This is because the first chip is attached to the die pad in a surface-to-surface manner having a large contact area between the first chip and the die pad, such that mismatch in coefficient of thermal expansion (CTE) between the first chip and the die pad tends to make the first chip delaminated from the die pad under temperature variations during the packaging processes, thereby resulting in degraded reliability of the fabricated package.
Consequently, U.S. Pat. No. 6,087,715 provides a lead frame having a separated die pad in order to solve the foregoing delamination problem. This die pad is formed with at least one opening therein to divide the die pad into a plurality of mounting portions for mounting at least one semiconductor chip thereon, such that the contact area between the semiconductor chip and the die pad is reduced, and delamination between the semiconductor chip and the die pad caused by thermal stress generated from thermal treatment of the packaging processes can be avoided.
FIG. 2A is a top view of a lead frame 20 having a separated die pad 200, and FIG. 2B is a cross-sectional view of a semiconductor package integrated with the lead frame 20 shown in FIG. 2A. Referring to FIGS. 2A and 2B, the separated die pad 200 of the lead frame 20 comprises a first mounting portion 201 and a second mounting portion 202, for allowing a first chip 21 to be attached to the top side of both the first and second mounting portions 201, 202 and allowing a second chip 22 to be attached to the bottom side of both the first and second mounting portions 201, 202. The first and second chips 21, 22 are electrically connected to leads 203 of the lead frame 20 by bonding wires. And an encapsulant 29 is formed to encapsulate the first chip 21, the second chip 22, and the die pad 200. Due to the separated die pad comprising a plurality of mounting portions, the contact area between the chips and the die pad is reduced, and thus thermal stress and delamination between the chips and the die pad can be moderated.
Further in the above lead frame with the separated die pad, a gap 25 is formed between the first chip 21 and the second chip 22 after they are mounted to the die pad 200. However, during a molding process for forming the encapsulant 29, an encapsulating resin injected into a mold cavity used in the molding process may change its flow rate when contacting the above components of the semiconductor package due to various factors such as the gap size, component surface planarity and so on.
FIGS. 3A and 3B are cross-sectional views showing mold flow situations in the molding process for the semiconductor package of FIG. 2B. As shown in FIGS. 3A and 3B, since the gap 25 between the first chip 21 and the second chip 22 is bordered by relatively smooth back surfaces of the first and second chips 21, 22 and does not have bonding wires or other elements therein, the flow of the encapsulating resin is relatively less impeded in the gap 25 and thus the encapsulating resin has a higher flow rate in the gap 25 than in gaps 27, 28 that are located between the chips 21, 22 and an encapsulation mold 26 respectively. This causes the following problem.
As the encapsulating resin injected from a gate G into the encapsulation mold 26 has a higher flow rate in the gap 25 than in the gaps 27, 28, when the encapsulating resin flowing through the gap 25 to a vent V at an end of the encapsulation mold 26, it would flow backwards into the gaps 27, 28. Since the vent V is blocked by the encapsulating resin flowing through the gap 25, air in the gaps 27, 28 cannot be expelled via the vent V but is compressed by the encapsulating resin flowing into the gaps 27, 28. The compressed air would impact the bonding wires that connect the chips 21, 22 to the lead frame, making the bonding wires deformed to cause short circuit between adjacent bonding wires.
Moreover, the air not able to be expelled through the vent remains in the encapsulant and forms voids 30, which would lead to a popcorn effect during subsequent thermal treatment and reliability testing, thereby degrading the quality of the semiconductor package.